A content addressable memory (CAM) device is a storage device having an array of memory cells that can be instructed to compare the specific pattern of a comparand word with data words stored in corresponding rows of the array. During a compare operation, the comparand word is provided to the CAM array and compared with all the CAM words. For each CAM word that matches the comparand word, a corresponding match line is asserted to indicate the match result. If any of the match lines are asserted, a match flag is typically asserted to indicate the match condition, and the match address or index of the highest priority matching entry in the CAM array is determined.
FIG. 1 shows a conventional binary CAM cell 100 including a memory cell 110 for storing a data bit D and a compare circuit 120 for comparing the data bit with a comparand bit C. Memory cell 110 includes a latch formed by cross-coupled inverters 112 and 114 that stores the data bit D at data node BLI and its complement at data node {overscore (BLI)}. Pass transistor 116 is coupled between node BLI and bit line BL, and has a gate coupled to a word line WL. Pass transistor 118 is coupled between node {overscore (BLI)} and complementary bit line {overscore (BL)}, and has a gate coupled to word line WL. Compare circuit 120 includes NMOS transistors 122, 124, 126, and 128. Transistors 122 and 124 are coupled in series between match line ML and ground potential, with the gate of transistor 122 receiving the data bit D from node BLI, and the gate of transistor 124 receiving the complement {overscore (C)} of the comparand bit from complementary comparand line {overscore (CL)}. Transistors 126 and 128 are coupled in series between match line ML and ground potential, with the gate of transistor 126 receiving the complement {overscore (D)} of the data bit from node {overscore (BLI)}, and the gate of transistor 128 receiving the comparand bit C from the comparand line CL. Having separate bit and comparand line pairs allows an array of CAM cells 100 to perform read and compare operations at the same time, which in turn may provide a performance advantage.
A weak PMOS pull-up transistor 10 is coupled between bit line BL and a supply voltage VDD, and has a gate coupled to ground potential to maintain transistor 10 in a conductive state. Similarly, a weak PMOS pull-up transistor 12 is coupled between complementary bit line {overscore (BL)} and VDD, and has a gate coupled to ground potential to maintain transistor 12 in a conductive state. Together, pull-up transistors 10 and 12 pre-charge the bit line pair BL and {overscore (BL)} toward VDD before and after read and write operations (e.g., when WL is de-asserted to logic low).
However, pull-up transistor 10 also pulls BL to a voltage between VDD and ground potential when BLI is a logic zero and WL is asserted to logic high (e.g., during read and write operations). Similarly, pull-up transistor 12 also pulls {overscore (BL)} to a voltage between VDD and ground potential when {overscore (BLI)} is a logic zero and WL is asserted to logic high. As a result, when simultaneously performing read and compare operations on CAM cell 100, bit line charge currents provided by pull-up transistors 10 and 12 may result in erroneous mismatch conditions indicated on the match line ML.
For example, during a compare operation between a logic low data bit D and a logic low comparand bit C (i.e., a match condition), CAM cell 100's internal data nodes BLI and {overscore (BLI)} are at approximately ground potential (D=0) and VDD ({overscore (D)}=1), respectively, and the match line ML is pre-charged to VDD by a well-known pre-charge circuit (not shown for simplicity). Comparand lines CL and {overscore (CL)} are driven to approximately ground potential (C=0) and VDD ({overscore (C)}=1), respectively. The logic high signals at node {overscore (BLI)} and on line {overscore (CL)} turn on transistors 126 and 124, respectively, and the logic low signals at node BLI and on line CL turn off transistors 122 and 128, respectively. Thus, because transistors 122 and 128 are non-conductive, compare circuit 120 does not discharge match line ML, which remains in its charged state to indicate the match condition.
If there is a concurrent read operation for CAM cell 100, the word line WL is driven to logic high to turn on pass transistors 116 and 118, which in turn couple the gate of transistor 122 to bit line BL and the gate of transistor 126 to complementary bit line {overscore (BL)}, respectively. Because pull-up transistor 10 remains conductive, data node BLI is undesirably charged towards VDD via pass transistor 116 and pull-up transistor 10 during the compare operation. As the voltage on node BLI approaches the threshold voltage VT of transistor 122, transistor 122 conducts a leakage current that begins discharging match line ML through transistor 124 towards ground potential. Thus, for a CAM array having many CAM cells 100 per row, the cumulative leakage current in compare circuits 120 of all CAM cells 100 in a selected row may sufficiently discharge the match line ML to erroneously indicate a mismatch condition for the row.
As semiconductor fabrication technologies become smaller, supply voltages and transistor threshold voltages become smaller, which in turn may exacerbate these undesirable leakage currents during concurrent read and compare operations. Further, when word line WL is selected for read and write operations, the conductive pull-up transistors 10 and 12 form current paths to ground potential through pass transistors 116 and 118 and the pull-down transistors (not shown) in inverters 112 and 114. These current paths to ground potential may result in undesirable power dissipation.
Like reference numerals refer to corresponding parts throughout the drawing figures.